Capstone Projects
Real-world VLSI design projects that prepare you for industry challenges
Intermediate
UART Controller Design
Universal Asynchronous Receiver-Transmitter implementation
Project Details:
- • Full-duplex serial communication
- • Configurable baud rates
- • Parity and stop bit support
- • FIFO buffers for data handling
Technologies:
VerilogSystemVerilogTestbench
Duration
3 weeks
Learning Outcomes:
- ✓ Understand serial communication protocols
- ✓ Design state machines
- ✓ Implement synchronization techniques
Advanced
AMBA AHB Protocol Implementation
ARM Advanced Microcontroller Bus Architecture protocol
Project Details:
- • Master-Slave architecture
- • Burst transfers support
- • Pipelined operation
- • Error handling mechanisms
Technologies:
SystemVerilogUVMProtocol Verification
Duration
4 weeks
Learning Outcomes:
- ✓ Master bus protocol design
- ✓ Implement complex handshaking
- ✓ Advanced verification techniques
Advanced
SIPM (Silicon Photomultiplier) Design
Sensor interface and signal processing module
Project Details:
- • Analog-to-digital conversion
- • Signal conditioning
- • Noise filtering
- • Data acquisition interface
Technologies:
Mixed-Signal DesignVerilog-ASimulation
Duration
5 weeks
Learning Outcomes:
- ✓ Understand sensor interfaces
- ✓ Mixed-signal design principles
- ✓ Signal processing techniques